USEIEEE.STD_LOGIC_1164.ALL
USEIEEE.STD_LOGIC_UNSIGNED.ALL
ENTITY CLOCK IS
PORT( CLK: IN STD_LOGIC
DOUT1:BUFFER STD_LOGIC_VECTOR( 3 DOWNTO 0) -----秒钟个位输出
DOUT2:BUFFER STD_LOGIC_VECTOR( 3 DOWNTO 0) -----秒钟时位输出
DOUT3:BUFFER STD_LOGIC_VECTOR( 3 DOWNTO 0) -----分钟个位输出
DOUT4:BUFFER STD_LOGIC_VECTOR( 3 DOWNTO 0) -----分钟时位输出
DOUT5:BUFFER STD_LOGIC_VECTOR( 3 DOWNTO 0) -----时钟个位输出
DOUT6: BUFFER STD_LOGIC_VECTOR( 3 DOWNTO 0) -----时钟十位输出
CO: OUT STD_LOGIC)
-- LED1: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0)
-- LED2: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0)
-- LED3: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0)
-- LED4: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0)
-- LED5: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0)
-- LED6: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0))
END CLOCK
ARCHITECTURECK OF CLOCK IS
SIGNAL CO1: STD_LOGIC
SIGNAL CO2: STD_LOGIC
SIGNAL QOUT1: STD_LOGIC_VECTOR( 3 DOWNTO 0)
SIGNAL QOUT2: STD_LOGIC_VECTOR( 3 DOWNTO 0)
SIGNAL QOUT3: STD_LOGIC_VECTOR( 3 DOWNTO 0)
SIGNAL QOUT4: STD_LOGIC_VECTOR( 3 DOWNTO 0)
SIGNAL QOUT5: STD_LOGIC_VECTOR( 3 DOWNTO 0)
SIGNAL QOUT6: STD_LOGIC_VECTOR( 3 DOWNTO 0)
-- COMPONENT LED IS
--PORT( QIN: STD_LOGIC_VECTOR(3 DOWNTO 0)
--QOUT: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0))
--END COMPONENT
BEGIN
U1: PROCESS( CLK ) ---秒钟进程表
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF QOUT1 = 9 THEN
IF QOUT2=5 THEN
CO1 <= '1'
QOUT1 <="0000"
QOUT2 <="0000"
ELSE
QOUT1 <= "0000"
CO1 <='0'
QOUT2 <= QOUT2+1
END IF
ELSE
QOUT1 <= QOUT1+1
CO1 <= '0'
END IF
END IF
END PROCESS
DOUT1 <= QOUT1
DOUT2 <= QOUT2
U2: PROCESS(CO1) --分钟进程表
BEGIN
IF CO1'EVENT AND CO1='1' THEN
IF QOUT3 = 9 THEN
IF QOUT4=5 THEN
CO2 <= '1'
QOUT3 <="0000"
QOUT4 <="0000"
ELSE
QOUT3 <= "0000"
CO2 <='0'
QOUT4 <= QOUT4+1
END IF
ELSE
QOUT3 <= QOUT3+1
CO2 <= '0'
END IF
END IF
END PROCESS
DOUT3 <= QOUT3
DOUT4 <= QOUT4
U3: PROCESS(CO2) --分钟进程表
BEGIN
IF CO2'EVENT AND CO2='1' THEN
IF QOUT5 = 3 THEN
IF QOUT6=2 THEN
CO <= '1'
QOUT5 <="0000"
QOUT6 <="0000"
ELSE
QOUT5 <= "0000"
CO <='0'
QOUT6 <= QOUT6+1
END IF
ELSE
QOUT5 <= QOUT5+1
CO <= '0'
END IF
END IF
END PROCESS
DOUT5 <= QOUT5
DOUT6 <= QOUT6
--L1: LEDPORT MAP( DOUT1,LED1)
--L2: LEDPORT MAP( DOUT2,LED2)
--L3: LEDPORT MAP( DOUT3,LED3)
--L4: LEDPORT MAP( DOUT4,LED4)
--L5: LEDPORT MAP( DOUT5,LED5)
--L6: LEDPORT MAP( DOUT6,LED6)
END ARCHITECTURE CK
下面是共阴数码管的程序
LIBRARY IEEE
USEIEEE.STD_LOGIC_1164.ALL
USEIEEE.STD_LOGIC_UNSIGNED.ALL
ENTITY LED IS ------共阴管
PORT( QIN: STD_LOGIC_VECTOR(3 DOWNTO 0)
QOUT: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0))
END LED
ARCHITECTURE DISPLAY OF LED IS
BEGIN
WITH QIN SELECT
QOUT <= "11111110" WHEN "0000",
"01100000" WHEN "0001",
"11011010" WHEN "0010",
"11110010" WHEN "0011",
"01100110" WHEN "0100",
"10110110" WHEN "0101",
"00111110" WHEN "0110",
"11100000" WHEN "0111",
"11111110" WHEN "1000",
"11100110" WHEN "1001",
"00000000" WHEN OTHERS
END ARCHITECTURE DISPLAY
这个是一个时钟程序；再加一个数码管显示就可以到数码管上显示出来了
这个电子钟是用六十进制和二十四进制写的
顶层文件：
LIBRARY IEEE
USEIEEE.STD_LOGIC_1164.ALL
USEIEEE.STD_LOGIC_UNSIGNED.ALL
ENTITY CLOCK IS
PORT( CLK: IN STD_LOGIC
CLR: IN STD_LOGIC
RES: IN STD_LOGIC
RES1 : IN STD_LOGIC_VECTOR( 5 DOWNTO 0)--秒钟重调
RES2 : IN STD_LOGIC_VECTOR( 5 DOWNTO 0)--分钟重调
RES3 : IN STD_LOGIC_VECTOR( 4 DOWNTO 0)--时钟重调
QO1 : OUT STD_LOGIC_VECTOR( 5 DOWNTO 0)-- 秒钟输出
QO2 : OUT STD_LOGIC_VECTOR( 5 DOWNTO 0)--分钟输出
QO3 : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0)--时钟输出
CO3 : OUT STD_LOGIC)
END ENTITY CLOCK
ARCHITECTURE TIME OF CLOCK IS
SIGNAL CO1: STD_LOGIC
SIGNAL CO2: STD_LOGIC
COMPONENT COUNT60 IS
PORT ( CLK : IN STD_LOGIC
CLR : IN STD_LOGIC
RES : IN STD_LOGIC
QIN : IN STD_LOGIC_VECTOR(5 DOWNTO 0)
QOUT : OUT STD_LOGIC_VECTOR( 5 DOWNTO 0)
CO : OUT STD_LOGIC )
END COMPONENT
COMPONENT COUNT24 IS
PORT ( CLK : IN STD_LOGIC
CLR : IN STD_LOGIC
RES : IN STD_LOGIC
QI : IN STD_LOGIC_VECTOR( 4 DOWNTO 0)
QO : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0)
CO : OUT STD_LOGIC )
END COMPONENT
BEGIN
U1: COUNT60
PORT MAP( CLK,CLR,RES,RES1,QO1,CO1)
U2: COUNT60
PORT MAP( CO1,CLR,RES,RES2,QO2,CO2)
U3: COUNT24
PORT MAP( CO2,CLR,RES,RES3,QO3,CO3)
END ARCHITECTURE TIME
下面是二十四进制计数
LIBRARY IEEE
USEIEEE.STD_LOGIC_1164.ALL
USEIEEE.STD_LOGIC_UNSIGNED.ALL
ENTITY COUNT24IS
PORT ( CLK : IN STD_LOGIC
CLR : IN STD_LOGIC
RES : IN STD_LOGIC
QI : IN STD_LOGIC_VECTOR( 4 DOWNTO 0)
QO : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0)
CO : OUT STD_LOGIC )
END ENTITY COUNT24
ARCHITECTURE BHV OF COUNT24 IS
SIGNAL Q : STD_LOGIC_VECTOR( 4 DOWNTO 0)
BEGIN
PROCESS( CLK, CLR, RES)
BEGIN
IF CLR = '1' THEN
Q <="00000"
ELSIF CLK'EVENT AND CLK='1' THEN
IF RES ='1' THEN
Q <=QI
ELSIF Q = 23 THEN
Q <="00000"
CO <='1'
ELSE Q <= Q+1
CO<='0'
END IF
END IF
END PROCESS
QO <= Q
END ARCHITECTURE BHV
下面是六十进制计数
LIBRARY IEEE
USEIEEE.STD_LOGIC_1164.ALL
USEIEEE.STD_LOGIC_UNSIGNED.ALL
ENTITY COUNT60 IS
PORT ( CLK : IN STD_LOGIC
CLR : IN STD_LOGIC
RES : IN STD_LOGIC
QIN : IN STD_LOGIC_VECTOR(5 DOWNTO 0)
QOUT : OUT STD_LOGIC_VECTOR( 5 DOWNTO 0)
CO : OUT STD_LOGIC )
END ENTITY COUNT60
ARCHITECTURE COUNT OF COUNT60 IS
SIGNAL Q : STD_LOGIC_VECTOR( 5 DOWNTO 0)
BEGIN
PROCESS (CLK,CLR,RES)
BEGIN
IF CLR = '1'THEN
Q <= "000000"
ELSIF CLK'EVENT AND CLK = '1' THEN
IF RES ='1' THEN
Q <= QIN
ELSIF Q = 59 THEN
Q <= "000000"
CO <='1'
ELSE
Q <=Q + 1
CO <= '0'
END IF
END IF
END PROCESS
QOUT <= Q
END ARCHITECTURE
这个是用两个60进制和一个24进制做的
图11程序如下：
library IEEE
use IEEE.STD_LOGIC_1164.ALL
use IEEE.STD_LOGIC_ARITH.ALL
use IEEE.STD_LOGIC_UNSIGNED.ALL
entity xuan21 is
Port ( alarm,a,b: in std_logic
y:out std_logic)
end xuan21
architecture one of xuan21 is
begin
process(alarm,a,b)
begin
if alarm='0' then y<=aelse y<=b
end if
end process
end one
仿真波形如下图12：
图12
（2）三位二选一：
模块图如图13。用以进行正常计时时间与闹铃时间显示的选择，alarm输入为按键。当alarm按键未曾按下时二选一选择器会选择输出显示正常的计时结果，否则当alarm按键按下时选择器将选择输出显示闹铃时间显示。
图13
程序如下：
library IEEE
use IEEE.STD_LOGIC_1164.ALL
use IEEE.STD_LOGIC_ARITH.ALL
use IEEE.STD_LOGIC_UNSIGNED.ALL
entity x213 is
Port ( alarm : in std_logic
y:out std_logic_vector(3 downto 0)
a,b: in std_logic_vector(3 downto 0))
end x213
architecture one of x213 is
begin
process(alarm,a,b)
begin
if alarm='0' then y<=aelse y<=b
end if
end process
end one
仿真结果如下图14：
图14
8、整点报时及闹时：
模块图如图15。在59分51秒、53秒、55秒、57秒给扬声器赋以低音512Hz信号,在59分59秒给扬声器赋以高音1024Hz信号,音响持续1秒钟,在1024Hz音响结束时刻为整点。当系统时间与闹铃时间相同时给扬声器赋以高音1024Hz信号。闹时时间为一分钟。
图15
程序如下：
library IEEE
use IEEE.STD_LOGIC_1164.ALL
use IEEE.STD_LOGIC_ARITH.ALL
use IEEE.STD_LOGIC_UNSIGNED.ALL
entity voice is
Port ( hou1,huo0,min1,min0,sec1,sec0,hh,hl,mh,ml: std_logic_vector(3 downto 0)
in_1000,in_500:in std_logic
q : out std_logic)
end voice
architecture one of voice is
begin
process(min1,min0,sec1,sec0)
begin
if min1="0101" and min0="1001" and sec1="0101" then
if sec0="0001" or sec0="0011" or sec0="0101" or sec0="0111"
then q<=in_500
elsif sec1="0101" and sec0="1001" then q<=in_1000
else q<='0'
end if
else q<='0'
end if
if min1=mh and min0=ml and hou1=hh and huo0=hl then
q<=in_1000
end if
end process
end one
仿真波形如下图16
图16
9、顶层原理图：
三、感想
通过这次设计，既复习了以前所学的知识，也进一步加深了对EDA的了解，让我对它有了更加浓厚的兴趣。特别是当每一个子模块编写调试成功时，心里特别的开心。但是在画顶层原理图时，遇到了不少问题，最大的问题就是根本没有把各个模块的VHD文件以及生成的器件都全部放在顶层文件的文件夹内，还有就是程序设计的时候考虑的不够全面，没有联系着各个模式以及实验板的情况来编写程序，以至于多考虑编写了译码电路而浪费了很多时间。在波形仿真时，也遇到了一点困难,想要的结果不能在波形上得到正确的显示
:在分频模块中，设定输入的时钟信号后，却只有二分频的结果，其余三个分频始终没反应。后来，在数十次的调试之后，才发现是因为规定的信号量范围太大且信号的初始值随机，从而不能得到所要的结果。还有的仿真图根本就不出波形，怎么调节都不管用，后来才知道原来是路径不正确，路径中不可以有汉字。真是细节决定成败啊！总的来说，这次设计的数字钟还是比较成功的，有点小小的成就感，终于觉得平时所学的知识有了实用的价值，达到了理论与实际相结合的目的，不仅学到了不少知识，而且锻炼了自己的能力，使自己对以后的路有了更加清楚的认识，同时，对未来有了更多的信心。
四、参考资料：
1、潘松，王国栋，VHDL实用教程〔M〕.成都:电子科技大学出版社，2000.(1)
2、崔建明主编，电工电子EDA仿真技术北京：高等教育出版社，2004
3、李衍编著，EDA技术入门与提高王行西安：西安电子科技大学出版社，2005
4、侯继红,李向东主编，EDA实用技术教程北京：中国电力出版社，2004
5、沈明山编著，EDA技术及可编程器件应用实训北京：科学出版社，2004
6、侯伯亨等，VHDL硬件描述语言与数字逻辑电路设计西安: 西安电子科技大学出版社，1997
7、辛春艳编著，VHDL硬件描述语言北京：国防工业出版社，2002 就这些
library ieeeuse ieee.std_logic_1164.all
use ieee.std_logic_arith.all
use ieee.std_logic_unsigned.all
--------------------------------------------------------------------
entity digital is
port( Clk : in std_logic --时钟输入
Rst : in std_logic --复位输入
S1,S2 : in std_logic --时间调节输入
led : out std_logic_vector(3 downto 0) --整点输报时输出
spk : out std_logic
Display : out std_logic_vector(6 downto 0) --七段码管显示输出
SEG_SEL : buffer std_logic_vector(2 downto 0) --七段码管扫描驱动
)
end digital
--------------------------------------------------------------------
architecture behave of digital is
signal Disp_Temp : integer range 0 to 15
signal Disp_Decode : std_logic_vector(6 downto 0)
signal SEC1,SEC10: integer range 0 to 9
signal MIN1,MIN10: integer range 0 to 9
signal HOUR1,HOUR10 : integer range 0 to 9
signal Clk1kHz: std_logic--数码管扫描时钟
signal Clk1Hz: std_logic--时钟计时时钟
signal led_count : std_logic_vector(2 downto 0)
signal led_display : std_logic_vector(3 downto 0)
signal spkcout: std_logic
begin
PROCESS(clk) --产生1hz信号
variable cnt : INTEGER RANGE 0 TO 49999999--产生1Hz时钟的分频计数器
BEGIN
IF clk='1' AND clk'event THEN
IF cnt=49999999 THEN cnt:=0
ELSE
IF cnt<25000000 THEN clk1hz<='1'
ELSE clk1hz<='0'
END IF
cnt:=cnt+1
END IF
END IF
end process
PROCESS(clk) --产生1hz信号
variable cnt1 : INTEGER RANGE 0 TO 49999--产生1KHz时钟的分频计数器
BEGIN
IF clk='1' AND clk'event THEN
IF cnt1=49999 THEN cnt1:=0
ELSE
IF cnt1<25000 THEN clk1khz<='1'
ELSE clk1khz<='0'
END IF
cnt1:=cnt1+1
END IF
END IF
end process
process(Clk1Hz,Rst)
begin
if(Rst='0') then--系统复位
SEC1<=0
SEC10<=0
MIN1<=0
MIN10<=0
HOUR1<=0
HOUR10<=0
elsif(Clk1Hz'event and Clk1Hz='1') then--正常运行
if(S1='0') then --调节小时
if(HOUR1=9) then
HOUR1<=0
HOUR10<=HOUR10+1
elsif(HOUR10=2 and HOUR1=3) then
HOUR1<=0
HOUR10<=0
else
HOUR1<=HOUR1+1
end if
elsif(S2='0') then --调节分钟
if(MIN1=9) then
MIN1<=0
if(MIN10=5) then
MIN10<=0
else
MIN10<=MIN10+1
end if
else
MIN1<=MIN1+1
end if
elsif(SEC1=9) then
SEC1<=0
if(SEC10=5) then
SEC10<=0
if(MIN1=9) then
MIN1<=0
if(MIN10=5) then
MIN10<=0
if(HOUR1=9) then
HOUR1<=0
HOUR10<=HOUR10+1
elsif(HOUR10=2 and HOUR1=3) then
HOUR1<=0
HOUR10<=0
else
HOUR1<=HOUR1+1
end if
else
MIN10<=MIN10+1
end if
else
MIN1<=MIN1+1
end if
else
SEC10<=SEC10+1
end if
else
SEC1<=SEC1+1
end if
end if
end process
process(Clk)--整点报时
begin
if(Clk1hz'event and Clk1hz='1') then
if(MIN10=5 and MIN1=9 and SEC10=5 and sec1>3) then--在59分55秒开始提示
led_Count<=led_Count+1spkcout<=not spkcout
else
led_count<="000"
spkcout<='0'
end if
spk<=spkcout
end if
end process
process(led_count)--整点报时LED灯的闪烁
begin
case (led_count) is
when "000"=>led_display<="0000"
when "001"=>led_display<="1111"
when "010"=>led_display<="0111"
when "011"=>led_display<="0011"
when "100"=>led_display<="0001"
when "101"=>led_display<="1111"
when others=>led_display<="0000"
end case
led<=led_display
end process
process(SEG_SEL)
begin
case (SEG_SEL+1) is
when "111"=>Disp_Temp<=HOUR10
when "110"=>Disp_Temp<=HOUR1
when "101"=>Disp_Temp<=10
when "100"=>Disp_Temp<=MIN10
when "011"=>Disp_Temp<=MIN1
when "010"=>Disp_Temp<=10
when "001"=>Disp_Temp<=SEC10
when "000"=>Disp_Temp<=SEC1
end case
end process
process(Clk1khz)
begin
if(Clk1khz'event and Clk1khz='1') then--扫描累加
SEG_SEL<=SEG_SEL+1
Display<=Disp_Decode
end if
end process
process(Disp_Temp) --显示转换
begin
case Disp_Temp is
when 0=>Disp_Decode<="0111111" --0
when 1=>Disp_Decode<="0000110" --1
when 2=>Disp_Decode<="1011011" --2
when 3=>Disp_Decode<="1001111" --3
when 4=>Disp_Decode<="1100110" --4
when 5=>Disp_Decode<="1101101" --5
when 6=>Disp_Decode<="1111101" --6
when 7=>Disp_Decode<="0000111" --7
when 8=>Disp_Decode<="1111111" --8
when 9=>Disp_Decode<="1101111" --9
when 10=>Disp_Decode<="1000000" ---
when others=>Disp_Decode<="0000000" --全灭
end case
end process
end behave
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