input a,
input b,
input c,
output y
)
assign y=~(a&b&c)
endmodule
ENTITY nand3 ISPORT (in1,in2,in3: IN bity: OUT bit)
END nand3
ARCHITECTURE rtl OF nand3 IS
BEGIN
y <= NOT (in1 AND in2 AND in3)
END rtl
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input a,
input b,
input c,
output y
)
assign y=~(a&b&c)
endmodule
ENTITY nand3 ISPORT (in1,in2,in3: IN bity: OUT bit)
END nand3
ARCHITECTURE rtl OF nand3 IS
BEGIN
y <= NOT (in1 AND in2 AND in3)
END rtl
欢迎分享,转载请注明来源:内存溢出
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